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     Journal Publications (SCI)

　

2024

　

，    Hwaseok Shin, Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin

Sim, Junseob So, Taehwan Kim, and Chulwoo Kim, "A 28-Gb/s Single-Ended PAM-4 Transceiver with Active-Inductor Equalizer and Amplitude-

Detection LSB Decoder for Memory Interfaces," accepted for IEEE Transactions on VLSI Systems.

　

，    Jincheol Sim, Changmin Sim, Jonghyuck Choi, Seungwoo Park, Seongcheol Kim, and Chulwoo Kim, "A 50Gb/s PAM-4 Transceiver with High-

Swing Driver, Dual-Loop Analog Equalizer, and Integrator-Based Baud-Rate Linear CDR for Short-Reach Links," accepted for IEEE Transactions

 on Circuits and Systems I.

　

，    Hyunjin Kim, Taehyeong Park, Seokjin Kim, Seokhee Han, Mingi Jeong, Jaekyun Kim, Inho Park, and Chulwoo Kim, "An Asynchronous

Geometric Sequence Array-Based Binary Search Digital Low-Dropout Regulator for O(log n)-Complexity Searching Operations," accepted for IEEE

Transactions on Power Electronics.

　

，    Junyoung Maeng, Inho Park, Jinwoo Jeon, Hyunjin Kim, Hoi Lee, and Chulwoo Kim, "A Tri-Mode Reconfigurable DC-DC Converter With

Photovolatic Energy Harvesting for Miniature IoT Batteries," accepted for IEEE Transactions on Circuits and Systems II.

　

，    Yoonjae Choi, Changmin Sim, Jonghyuck Choi, Jincheol Sim, Hyunsu Park, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, and Chulwoo

 Kim, "A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory

Interfaces," accepted for IEEE Transactions on Circuits and Systems I.

　

，    Hyunjin Kim, Taehyeong Park, Inho Park, Changhun Park, Seokjin Kim, Seokhee Han, Junwon Jeong, and Chulwoo Kim, "A Fully Integrated

Nine-Ratio Switched-Capacitor Converter with Overlapped-Conversion-Ratio Modulation for IoT Applications," IEEE Journal of Solid-State Circuits,

vol. 59, no .10, pp. 3444-3456, Oct. 2024.

　

，    Seongcheol Kim, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Changmin Sim, Junseob So, Taehyeong

Park, and Chulwoo Kim, "Single-Ended PAM-4 Transmitters with Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces,"

IEEE Journal of Solid-State Circuits, vol. 59, no .10, pp. 3432-3443, Oct. 2024.

　

，    Seongcheol Kim, Changmin Sim, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Junseob So, Hwaseok Shin, Seon-Been

Lee, and Chulwoo Kim, "A 0.458-pJ/bit 24-Gb/s/pin Capacitively-Driven PAM-4 Transceiver with PAM-Based Crosstalk Cancellation for High Density

Die-to-Die Interfaces," accepted for IEEE Journal of Solid-State Circuits.

　

，    Yohan Choi, Woojin Lee, Sooho Park, Changjoo Kim, Hyundo Jung, and Chulwoo Kim, "A 101.6-dB-SNDR Fully Dynamic Zoom ADC Using

Miller-Compensated Floating Inverter Amplifiers," IEEE Transactions on Circuits and Systems II, vol. 71, no. 9, pp. 4141-4145, Sep. 2024.

　

，    Seungwoo Park, Yoonjae Choi, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seongcheol Kim, Changmin Sim, and Chulwoo Kim,

"A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling," IEEE Transactions on Circuits and Systems II, vol. 71,

no. 9, pp. 4096-4100, Sep. 2024.

　

，    Taehyeong Park, Hyunjin Kim, Inho Park, Mingi Jeong, and Chulwoo Kim, "A Fully Integrated Dual-Output Continuously Scalable-Conversion-

Ratio SC Converter for battery Powered IOT Applications," IEEE Transactions on Circuits and Systems I, vol. 71, no. 8, pp. 3463-3475, Aug. 2024.

　

，    Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, Hwaseok Shin, Junseob So, Seon-Been

Lee, and Chulwoo Kim, "A Wireline Transceiver with 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling

Techniques,"IEEE Journal of Solid-State Circuits, vol. 59, no .8, pp. 2518-2528, Aug. 2024.

　

，    Hyoshin Kang, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, and

Chulwoo Kim, "A 13-Gb/s Single-Ended NRZ Receiver with 1-Sample per 2-UI Using Data Edge Sampling for Memory Interfaces," IEEE

Transactions on Circuits and Systems II, vol. 71, no. 7, pp. 3328-3332, Jul. 2024.

　

，    Jincheol Sim, Changmin Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Jong-Min

Kim, Ju-Hyung Lee, Young-Chai Ko, and Chulwoo Kim, "A 10 Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free

Space Optical Communication Over 10 m and 100 m Distance,"  IEEE Journal of Solid-State Circuits, vol. 59, no. 6, pp. 1835-1846, Jun. 2024.

　

，    Junyoung Maeng, Junwon Jeong, Inho Park, Minseob Shim, and Chulwoo Kim, "A Time- Based Direct MPPT Technique for Low-Power

 Photovoltaic Energy Harvesting," IEEE Transactions on Industrial Electronics, vol. 71, no. 5, pp. 5375-5380, May 2024.

　

，    Jonghyuck Choi, Yoonjae Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, and Chulwoo Kim,

"A Single-Ended NRZ Receiver with Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces," IEEE Journal of

Solid-State Circuits, vol. 59, no .4, pp. 1261-1270, Apr. 2024.

　

，    Hyunjin Kim, Changhun Park, Inho Park, Taehyeong Park, Seungwoo Park, and Chulwoo Kim, "A Four-Phase Time-Based Switched-Capacitor

LDO with 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications," IEEE Journal of Solid-State Circuits, vol. 59, no .2,

pp. 551-562, Feb. 2024.

　

2023

　

，    Inho Park, Hyunjin Kim, Taehyeong Park, Junwon Jeong, and Chulwoo Kim, "An Automotive 12 V-to-1.2 V Integrated Switched-Capacitor DC–DC

Converter for Improved Load Transient Response,"  IEEE Transactions on Power Electronics, vol. 38, no. 10, pp. 12315-12319, Oct. 2023.

　

，    Hyundo Jung, Hyunjin Kim, Woojin Lee, Jinwoo Jeon, Yohan Choi, Taehyeong Park, and Chulwoo Kim, "A quantum-inspired probabilistic prime

factorization based on virtually connected Boltzmann machine and probabilistic annealing," Scientific Reports 13, 16186, Sep. 2023.

　

，    Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, and Chulwoo Kim, "A 33 Gb/s/pin 1.09 pJ/bit

Single-Ended PAM-3 Transceiver with Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory

Interface," IEEE Journal of Solid-State Circuits, vol. 58, no .8, pp. 2314-2325, Aug. 2023.

　

，    Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Changmin Sim, and Chulwoo Kim, "A 4-GHz

Ring-Oscillator-Based Digital Sub-Sampling PLL with Energy-Efficient Dual-Domain Phase Detector," IEEE Transactions on Circuits and Systems

I, vol. 70, no. 7, pp. 2734-2743, Jul. 2023.

　

，    Yoonjae Choi, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, Changmin Sim, and Chulwoo

Kim, "A 25Gb/s Single-Ended PAM-4 Receiver with Time-Windowed LSB Decoder for High-Speed Memory Interfaces," IEEE Journal of Solid-State

Circuits, vol. 58, no .7, pp. 2005-2015, Jul. 2023.

　

，    Inho Park, Jinwoo Jeon,  Hyunjin Kim, Taehyeong Park, Junwon Jeong, and Chulwoo Kim, "A Thermoelectric Energy-Harvesting Interface with

Dual-Conversion Reconfigurable DC-DC Converter and Instantaneous Linear Extrapolation MPPT Method," IEEE Journal of Solid-State Circuits

, vol. 58, no .6, pp. 1706-1718, Jun. 2023.

　

，    Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, and Chulwoo Kim, "PAM-4 Receiver with 1-Tap DFE using

Clocked Comparator Offset instead of Threshold Voltages for Improved LSB BER performance,"  IEEE Transactions on Circuits and Systems I,

vol. 70, no. 5, pp. 1907-1916, May 2023.

　

，    Jonghyuck Choi, Yoonjae Choi, Hyunsu Park, Jincheol Sim, Youngwook Kwon, Seungwoo Park, Seongcheol Kim, and Chulwoo Kim, "A 16-Gb/s

NRZ Receiver with 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE,"  IEEE Transactions on Circuits and Systems II, vol. 70, no. 3, pp. 904-908,

Mar. 2023.

　

，    Seongcheol Kim, Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, and Chulwoo Kim, "A 15-Gb/s Single-Ended NRZ Receiver Using

Self-Referenced Technique with 1-Tap Latched DFE for DRAM Interfaces,"  IEEE Transactions on Circuits and Systems II, vol. 70, no. 1, pp. 101-

105, Jan. 2023.

　

2022

　

，    Chaegang Lim, Yohan Choi, Jaegeun Song, Soonsung Ahn, Seokwon Jang, and Chulwoo Kim, "An 88.9 dB SNR Fully-Dynamic Noise-Shaping

SAR Capacitance-to-Digital Converter," IEEE Journal of Solid-State Circuits, vol. 57, no. 9, pp. 2778-2790, Sep. 2022.

　

，    Jonghyuck Choi, Yoonjae Choi, Hyunsu Park, Jincheol Sim, Youngwook Kwon, Seungwoo Park, and Chulwoo Kim, "Analysis of a Multi-Wire,

Multi-Level, and Symbol Correlation Combination Scheme," IEEE Transactions on Circuits and Systems I, vol. 69, no. 8, pp. 3416-3427, Aug.

2022.

　

，    Youngwook Kwon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Seungwoo Park, and Chulwoo Kim, "A 15 Gb/s Non-return-to-

zero Transmitter with 1-tap Pre-emphasis Feed-forward Equalizer for Low-power Ground Terminated Memory Interfaces," IEEE Transactions on

Circuits and Systems II, vol. 69, no. 6, pp. 2737-2741, Jun. 2022.

　

，    Jaegeun Song, Yunsoo Park, Chaegang Lim, Yohan Choi, Soonsung Ahn, Sooho Park, and Chulwoo Kim, "A 9-bit 500-MS/s 2-bit/cycle SAR

ADC With Error-Tolerant Interpolation Technique," IEEE Journal of Solid-State Circuits, vol. 57, no. 5, pp. 1492-1503, May 2022.

　

，     Kungryun Yoon, Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, and Chulwoo Kim, "A 4.5 Gb/s/pin transceiver with hybrid ISI and

FEXT equalization for next-generation HBM interface,"  IET Electronics Letters, vol. 58, no. 11, pp. 420-422, Apr. 2022.

　

，    Inho Park, Junyoung Maeng, Jinwoo Jeon, Hyunjin Kim, and Chulwoo Kim, "A Four-Phase Hybrid Step-Up/-Down Converter with RMS Inductor

Current Reduction and Delay-Based Zero-Current," IEEE Transactions on Power Electronics, vol. 37, no. 4, pp. 3708-3712, Apr. 2022.

　

，    Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, and Chulwoo Kim, "A 2.4–8 GHz Phase Rotator Delay-Locked

Loop Using Cascading Structure for Direct Input–Output Phase Detection," IEEE Transactions on Circuits and Systems II, vol. 69, no. 3, pp. 794-

798, Mar. 2022.

　

，    Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Youngwook Kwon, and Chulwoo Kim, "A 56-Gb/s PAM-4 Receiver using Time-

Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations," IEEE Journal of Solid-State Circuits, vol. 57, no. 2,

pp. 562-572, Feb. 2022.

　

，    Jincheol Sim, Yeonho Lee, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, and Chulwoo Kim, "A 25 Gb/s Wireline Receiver with

Feedforward and Feedback Equalizers at Analog Front-End," IEEE Transactions on Circuits and Systems II, vol. 69, no. 2, pp. 404-408, Feb. 2022.

　

2021

　

，    Minsu Jeong, Eunsu Kim, Ook Hong, and Chulwoo Kim, "A 0.37-in. 5900PPI Liquid Crystal on Silicon CMOS SoC using Low Voltage High

Dynamic Voltage Range Novel Pixel Circuit for Augmented Reality Micro-Displays," Journal of the Society for Information Display, vol. 29, no. 10,

pp. 785-792, Oct. 2021.

　

，    Yoonjae Choi, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, and Chulwoo Kim, "A 0.99-pJ/b 15-Gb/s Counter-

Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS," IEEE Transactions on Circuits and Systems II, vol. 68, no. 10, pp. 3189-

3193, Oct. 2021.

　

，    Yoonjae Choi, Sewook Hwang, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, and Chulwoo Kim, "A 1.69-pJ/b 14-Gb/s Digital Sub

-Sampling CDR with Combined Adaptive Equalizer and Self-Error Corrector," IEEE Access, vol. 9, pp. 118907-118918, Sep. 2021.

　

，    Hyunjin Kim, Junyoung Maeng, Inho Park, Jinwoo Jeon, Yohan Choi, and Chulwoo Kim, "A Dual-Mode Continuously Scalable-Conversion-Ratio

SC Energy Harvesting Interface with SC-based PFM MPPT and Flying Capacitor Sharing Scheme," IEEE Journal of Solid-State Circuits, vol. 56,

no. 9, pp. 2724-2735, Sep. 2021.

　

，    Junyoung Song, Sewook Hwang, and Chulwoo Kim, "A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only

Equalization in 65-nm CMOS Technology," IEEE Transactions on Very Large Scale Integration Systems, vol. 29, no. 8, pp. 1567-1574, Aug. 2021.

　

，    Chaegang Lim, Yohan Choi, Yunsoo Park, Jaegeun Song, Soonsung Ahn, Sooho Park, and Chulwoo Kim, "A Capacitively Coupled CTツヒM

with Chopping Artifacts Rejection for Sensor Readout ICs," IEEE Transactions on Circuits and Systems I, vol. 68, no. 8, pp. 3242-3253, Aug. 2021.

　

，    Hyunsu Park, Jincheol Sim, Yoonjae Choi, Jonghyeok Choi, Youngwook Kwon, Seungwoo Park, Gyutae Park, Jinil Chung, Kyeong-Min Kim,

Hae-Kang Jung, Hyungsoo Kim, Junhyun Chun, and Chulwoo Kim, "A 1.3-4 GHz Quadrature-Phase Digital DLL Using Sequential Delay Control

and Reconfigurable Delay Line," IEEE Journal of Solid-State Circuits, vol. 56, no. 6, pp. 1886-1896, Jun. 2021.

　

，    Hyunjin Kim, Junyoung Maeng, Inho Park, Jinwoo Jeon, Dongju Lim, and Chulwoo Kim, "A 90.2% Peak Efficiency Multi-Input Single-Inductor

Multi-Output Energy Harvesting Interface With Double-Conversion Rejection Technique and Buck-Based Dual-Conversion Mode," IEEE

Journal of Solid-State Circuits, vol. 56, no. 3, pp. 961-971, Mar. 2021.

 

，    Junyoung Maeng, Inho Park, Minseob Shim, Junwon Jeong, and Chulwoo Kim, "A High-Voltage Dual-Input Buck Converter With Bidirectional

 Inductor Current for Triboelectric Energy-Harvesting Applications," IEEE Journal of Solid-State Circuits, vol. 56, no. 2, pp. 541-553, Feb. 2021.

　

，    Hyunsu Park, Junyoung Song, Jincheol Sim, Yoonjae Choi, Jonghyuck Choi, Jeongsik Yoo, and Chulwoo Kim, "30-Gb/s 1.11-pJ/bit

Single-ended PAM-3 Transceiver for High-speed Memory Links," IEEE Journal of Solid-State Circuits, vol. 56, no. 2, pp. 581-590, Feb. 2021.

　

，    Junyoung Maeng, Minseob Shim, Junwon Jeong, Inho Park, and Chulwoo Kim, "A Periodically Refreshed Capacitive Floating Level Shifter for

Conditional Switching Applications," IEEE Transactions on Power Electronics, vol. 36, no. 2, pp.1264-1268, Feb. 2021.

　

2020

　

，    Youngbog Yoon, Hyunsu Park, and Chulwoo Kim, " A DLL-based Quadrature Clock Generator with a 3-stage Quad Delay Unit using the

Sub-range Phase Interpolator for Low-jitter and High-phase Accuracy DRAM Applications," IEEE Transactions on Circuits and Systems II, vol. 67,

no. 11, pp. 2342-2346, Nov. 2020.

　

，    Youngbog Yoon, and Chulwoo Kim, "An Area-efficient and Wide-range Inter-signal Skew Compensation Scheme with the Embedded Bypass

Control Register Operating as a Binary Search Algorithm for DRAM Applications," IEEE Transactions on Circuits and Systems II, vol. 67, no. 10,

pp. 1775-1779, Oct. 2020.

　

，    Yunsoo Park, Jaegeun Song, Yohan Choi, Chaegang Lim, Soonsung Ahn, and Chulwoo Kim, "An 11-b 100MS/s Fully Dynamic Pipelined

ADC Using a High-linearity Dynamic Amplifier," IEEE Journal of Solid-State Circuits, vol. 55, no. 6, pp. 2468-2477, Sep. 2020.

　

，    Eunhee Kim, and Chulwoo Kim, "A Digital LDO Regulator with Analog-Assisted Loop using Source Follower," IET Electronics Letters, vol. 56,

no. 16, pp. 801-803, Aug. 2020.

　

，    Jaegeun Song, Jaehun Jun, and Chulwoo Kim, "A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold

Voltage-Optimized Design Technique," IEEE Transactions on Circuits and Systems II, vol. 67, no.7, pp. 1184-1188, Jul. 2020.

　

，    Junyoung Maeng, Minseob Shim, Junwon Jeong, Inho Park, Yunsoo Park, and Chulwoo Kim, " A Sub-fs-FoM Digital LDO Using PMOS and

 NMOS Arrays With Fully Integrated 7.2-pF Total Capacitance," IEEE Journal of Solid-State Circuits, vol. 55, no. 6, pp. 1624-1636, Jun. 2020.

　

，    Inho Park,  Junyoung Mang, Minseob Shim, and Chulwoo Kim, "A High-Voltage Dual-Input Buck Converter Achieving 52.9% Maximum

End-to-End Efficiency for Triboelectric Energy Harvesting," IEEE Journal of Solid-State Circuits, vol. 55, no. 5, pp. 1324-1336, May 2020.

　

，    Jaehun Jun, Sangsu Lee, and Chulwoo Kim, "Near threshold voltage digital PLL using low voltage optimised blocks for AR display system,"

IET Circuits, Devices & Systems, vol. 14, no. 2, pp. 155-158, Mar. 2020.

　

，    Junwon Jeong, Minseob Shim, Junyoung Maeng, Inho Park, and Chulwoo Kim, " An Efficiency-Aware Cooperative Multicharger System for

Photovoltaic  Energy Harvesting Achieving 14% Efficiency Improvement," IEEE Transactions on Power Electronics, vol. 35, no. 3, pp. 2253-2256,

Mar. 2020.

　

，    Junwon Jeong, Minseob Shim, Junyoung Maeng, Inho Park, and Chulwoo Kim, " A High-Efficiency Charger With Adaptive Input Ripple MPPT for

Low-Power Thermoelectric Energy Harvesting Achieving 21% Efficiency Improvement," IEEE Transactions on Power Electronics, vol. 35, no. 1,

pp. 347-358, Jan. 2020.

　

2019

　

，    Dongju Lim, Manho Seung, Seokkiu Lee, and Chulwoo Kim, "A Parasitics-Induced Failure Mechanism for Transistors in the Bit-Line Sense

,Amplifier Region of DDP DDR3 DRAM during a CDM Event," IEEE Transactions on Device and materials Reliability, vol. 19, no. 4, pp 711-717,

Dec. 2019.

　

，    Junyoung Song, Yongtae Kim, and Chulwoo Kim, "A 9Gb/s/ch Transceiver with Reference-less Data-embedded Pseudo- differential

Clock Signaling for Graphics Memory Interfaces," IEEE Transactions on Circuits and Systems II, vol. 66, no. 12, pp. 1982-1986, Dec. 2019.

　

，    Minseob Shim, Junwon Jeong, Junyoung Maeng, Inho Park, and Chulwoo Kim, "Fully Integrated Low-Power Energy Harvesting System With

Simplified Ripple Correlation Control for System-on-a-Chip Applications," IEEE Transactions on Power Electronics, vol. 34, no. 5, pp. 4353-4361

May 2019.

　

，    Yeonho Lee, Yoonjae Choi, Jonghyuk Choi, and Chulwoo Kim, ＾24-Gb/s Input-Data-Independent Clock and Data Recovery Utilizing Bit-Efficient

Braid Clock Signaling with Fixed Embedded Transition for 8K-UHD intra-panel Interface," IEEE Solid-State Circuit Letters, vol. 2, no. 3, pp. 21-24,

Mar. 2019.

　

，    Yeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, and Chulwoo Kim, "12Gb/s Over Four Balanced

Lines Utilizing NRZ Braid Clock Signaling with 100% Data Payload and Spread Transition Scheme for 8K UHD Intra-panel Interfaces," IEEE

Journal of Solid-State Circuits, vol. 54, no. 2, pp. 463-475, Feb. 2019.

　

，    Junwon Jeong, Seokhyun Jeong, Dennis Sylvester, David Blaauw, and Chulwoo Kim, "A 42nJ/conversion On-Demand

State-of-Charge Indicator for Miniature IoT Li-ion Batteries," IEEE Journal of Solid-State Circuits, vol. 54, no. 2, pp. 524-237, Feb. 2019.

　

，    Sang-Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, and Chulwoo Kim, "A ツヒ-Modulator based Spread-Spectrum Clock

Generator with Digital Compensation and Calibration for PLL Loop Bandwidth," IEEE Transactions on Circuits and Systems II, vol. 66, no. 2,

pp. 192-196, Feb. 2019.

　

2018

　

，    Jaehun Jun, Sang-Geun Bae, Yeonho Lee, and Chulwoo Kim, "A Spread Spectrum Clock Generator with Nested Modulation Profile for High-

Resolution Display System," IEEE Transactions on Circuits and Systems II, vol. 65, no. 11, pp. 1509-1513, Nov. 2018.

　

，    Jeongsik Yoo, Yeonho Lee, Yoonjae Choi, Hyunsu Park, Sanghun Park, and Chulwoo Kim, "A Low-Power Post-LPDDR4 Interface using AC

Termination at RX and An Active Inductor at TX," IEEE Transactions on Circuits and Systems II, vol. 65, no. 6, pp. 789-793, Jun. 2018.

　

，    Jaehun Jun, Jaegeun Song, and Chulwoo Kim, "A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized

Performance in 65nm CMOS process," IEEE Transactions on Circuits and Systems I, vol. 65, no. 5, pp. 1567-1580, May 2018.

　

，    Junyoung Song, Sewook Hwang, Hyun-Woo Lee, and Chulwoo Kim, "1-V 10-Gb/s/pin Single-Ended Transceiver with Controllable

Active-Inductor-Based Driver and Adaptively Calibrated Cascade-DFE for Post-LPDDR4 Interfaces," IEEE Transactions on Circuits and Systems I,

vol. 65, no. 1, pp. 331-342, Jan. 2018.

　

2017

　

，    Sewook Hwang, Sang-Geun Bae, Changsung Choi, Yeonho Lee, Junyoung Song, and Chulwoo Kim, "A 1.62-5.4 Gb/s Receiver for DisplayPort

Version 1.2a with Adaptive Equalization and Referenceless Frequency Acquisition Techniques," IEEE Transactions on Circuits and Systems I,

vol. 64, no. 10, pp. 2691-2702, Oct. 2017.

　

，    Jungtaek You, Junyoung Song, and Chulwoo Kim, "A 2Gb/s/ch Data-dependent Swing-limited On-chip Signaling for Single-ended Global I/O in

SDRAM,"  IEEE Transactions on Circuits and Systems II, vol. 64, no. 10, pp. 1207-1211, Oct. 2017.

　

，    Sang-Geun Bae, Gyungmin Kim, and Chulwoo Kim, "A 5-GHz Sub-Sampling PLL based Spread-Spectrum Clock Generator by Calibrating the

Frequency Deviation," IEEE Transactions on Circuits and Systems II, vol. 64, no. 10, pp. 1132-1136, Oct. 2017.

　

，    Young-Jae Min, Chan-Hui Jeong, Junil Moon, Youngsun Han, Soo-Won Kim, and Chulwoo Kim, "A 1.3V input fast-transient-response time

 digital low-dropout regulator with a VSSa generator for DVFS system," IEICE Electronics Express, vol. 14, no. 13, pp. 1-11, Jul. 2017

　

，    Ja-young Kim, Junyoung Song, Jungtaek You, Sewook Hwang, Sang-Geun Bae, and Chulwoo Kim, "A 250 Mb/s-to-6 Gb/s Reference-less Clock

and Data Recovery Circuit with Clock Frequency Multiplier," IEEE Transactions on Circuits and Systems II, vol. 64, no. 6, pp. 650-654, Jun. 2017.

　

，    Minseob Shim, Seokhyeon Jeong, Paul D. Myers, Suyoung Bang, Junhua Shen, Chulwoo Kim, Dennis Sylvester, David Blaauw, Wanyeong

Jung, "Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s

15 b SAR ADC," IEEE Journal of Solid-State Circuits, vol. 52, no. 4, pp. 1077-1090, Apr. 2017.

　

，    Sang-Geun Bae, Yongtae Kim, Yunsoo Park, and Chulwoo Kim,  "3Gb/s High-Speed True Random Number Generator Using Common-Mode

 Operating Comparator and Sampling Uncertainty of D Flip-Flop,"  IEEE Journal of Solid-State Circuits, vol. 52, no. 2, pp. 605-610, Feb. 2017.

　

，     Junyoung Song, Hyun-Woo Lee, Sewook Hwang, and Chulwoo Kim, "A 10Gb/s/pin DFE-less Graphics DRAM Interface with Adaptive-

bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique," IEEE Transactions on VLSI Systems, vol. 25, no. 1, pp. 344-353,

Jan. 2017.

　

2016

　

，    Jaehun Jun, Beomjin Kim, Sunkyung Shin, Kyungjin Jang, Jongsang Baek, and Chulwoo Kim, "In-cell Self-capacitive Type Mobile Touch System

 and Embedded Readout Circuit in Display Driver IC," IEEE Journal of Display Technology, vol. 12, no. 12, pp. 1613-1622, Dec. 2016.

　

，    Yunsoo Park, Jintae Kim, and Chulwoo Kim,  "A scalable bandwidth mismatch calibration technique for time-interleaved ADCs,"  IEEE

Transaction on Circuits and Systems I, vol. 63, no.11, pp. 1889-1897, Nov. 2016.

　

，    Chulwoo Kim, Hyun-Woo Lee, and Junyoung Song, "Memory Interfaces : Past, Present, and Future," IEEE Solid-State Circuits Magazine,  vol. 8,

 no. 2, pp. 23-24, Jun. 2016.(Invited)

　

，    Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, and Chulwoo Kim, "An Add-On Type Real-Time Jitter Tolerance Enhancer for

Digital Communication Receivers," IEEE Transactions on VLSI Systems, vol. 24, no. 3, pp. 1092-1103, Mar. 2016.

　

，    Junyoung Song, Sewook Hwang, and Chulwoo Kim, "A 4／5Gb/s 1.12us locking time Reference-less Receiver with Asynchronous Sampling-

based Frequency Acquisition and Clock Shared Sub-channels," IEEE Transactions on VLSI Systems, vol. 24, no. 8, pp. 2768-2777, Feb. 2016.

　

2015

　

，    Jaehong Ko, Chang-Ho An, Chan-Keun Kwon, Soo-Won Kim, Chulwoo Kim, "Rail-to-rail regulating voltage-controlled oscillator with low supply

and ground noise sensitivity," IET Electronics Letters, vol. 51, no. 24, pp. 1980-1982, Nov. 2015.

　

，    Hokyu Lee, Aurangozeb, Sejin Park, Jintae Kim, and Chulwoo Kim, "A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using

Resistor-Array Sharing Digital-to-Analog Converter," IEEE Transactions on VLSI Systems, vol. 23, no. 11, pp 2371-2383, Nov. 2015.

　

，    Minseob Shim, Jungmoon Kim, Junwon Jung, Sejin Park, and Chulwoo Kim, "Self-Powered 30-レW to 10-mW Piezoelectric Energy Harvesting

System with 9.09-ms/V Maximum Power Point Tracking Time," IEEE Journal of Solid State Circuits, vol. 50, no. 10, pp. 2367-2379, Oct. 2015.

　

，    Hyun Cheol Koo, Inhwa Jung, and Chulwoo Kim, "Spin-based complementary logic device using Datta-Das transistors," IEEE Transactions on

Electron Devices, vol. 62, no. 9, pp. 3056-3060, Sep. 2015.

　

，    Jaehong Ko, Chulwoo Kim, Soo-won Kim, "V-I converter-based voltage-controlled oscillator with improved linear gain characteristic," IET

Electronics Letters, vol. 51, no. 15, pp. 1211-1212, Jul. 2015.

　

，    Hokyu Lee, Sejin Park, Chaegang Lim, and Chulwoo Kim, "A 100-nW 9.1-ENOB 20-kS/s SAR ADC for portable Pulse Oximeter," IEEE

Transactions on Circuits and Systems II, vol. 62, no. 4, pp. 357-361, Apr. 2015.

　

2014

　

，    Jungmoon Kim, Philip K.T. Mok, and Chulwoo Kim, "A 0.15-V Input Energy Harvesting Charge Pump with Switching Body Biasing and Adaptive

Dead-Time for Efficiency Improvement," IEEE Journal of Solid-State Circuits, vol.50, no.2, pp.414-425, Feb. 2015.

　

，    Changsung Choi, Sewook Hwang, and Chulwoo Kim, "2.56 GHz sub-harmonically injection-locked PLL with cascaded DLL for multi-phase

injection," IET Electronics Letters, vol. 50, no. 24, pp. 1803-1804, Nov. 2014.

　

，    Junyoung Song, Sewook Hwang, Hyun-Woo Lee, and Chulwoo Kim " A 7.5Gb/s Reference-less Transceiver with Adaptive Equalization and

Bandwidth-Shifting Technique for Ultra High-Definition Television in 0.13um CMOS Process," IEEE Transactions on Circuits and

Systems II, vol. 61, no. 11, pp. 865-869,  Nov. 2014.

　

，    Kyeong-Min Kim, Sewook Hwang, Junyoung Song, and Chulwoo Kim, "A 11.2Gbps LVDS Receiver with a Wide Input Range Comparator," 

IEEE Transactions on VLSI Systems, vol. 22, no. 10, pp. 2156-2163, Oct. 2014.

　

，    Junyoung Song, and Chulwoo Kim, "A 6Gb/s Transmitter with Data-Dependent Jitter Reduction Technique for DisplayPort Physical Layer,"

Analog Integrated Circuits and Signal Processing, vol. 81, no. 2, pp. 529-536, Sep. 2014.

　

，    Sewook Hwang, Junyoung Song, Sang-Geun Bae, and Chulwoo Kim, "A 3Gb/s Transmitter with a Tapless Pre-Emphasis CML Output Driver,"

Analog Integrated Circuits and Signal Processing, vol. 81, no. 2, pp. 461-469, Sep. 2014.

　

，    Jungmoon Kim, Jihwan Kim, Minseob Shim, Soowon Kim, and Chulwoo Kim, "A single-input four-output (SIFO) AC-DC rectifying system

for vibration energy harvesting," IEEE Transactions on Power Electronics, vol. 29, no. 6, pp. 2629-2633, Jun. 2014.

　

，    Hyun-Woo Lee and Chulwoo Kim, "Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces," IEEE Transactions on VLSI

Systems, vol. 22, no. 4, pp. 701-711, Apr. 2014.

　

，    Junyoung Song, Sewook Hwang, Tae-Chan Kim, and Chulwoo Kim, "A 400 MHz-1.5 GHz all digital integer-N PLL with a reference spur

reduction technique," Analog Integrated Circuits and Signal Processing, vol. 79, no. 1, pp. 183-189, Feb. 2014.

　

2013

　

，    Jungmoon Kim, Dong Seok Kim, and Chulwoo Kim " A Single-Inductor Eight-Channel Output DC-DC Converter With Time-Limited

Power Distribution Control and Single Shared Hysteresis Comparator," IEEE Transactions on Circuits and Systems I, vol. 60, no. 12,

pp. 3354-3367, Dec. 2013.

　

，    Minyoung Song, Inhwa Jung, Sudhakar Pamarti, and Chulwoo Kim, "A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop With

Delay-Cell-Less TDC," IEEE Transactions on Circuits and Systems I,  vol. 60, no. 12, pp. 3145-3151, Dec. 2013.

　

，    Minyoung Song, Young-Ho Kwak, Sunghoon Ahn, Hojin Park, and Chulwoo Kim, "10-315-MHz Cascaded Hybrid Phase-Locked Loop

for Pixel Clock Generation," IEEE Transactions on VLSI Systems, vol. 21, no. 11, pp. 2080-2093, Nov. 2013.

　

，    Kisoo kim, Hokyu Lee, and Chulwoo Kim, "A 366-kS/s 1.09-nJ 0.0013-mm2 Frequency-to-Digital Converter Based CMOS Temperature

 Sensor Utilizing Multiphase Clock," IEEE Transactions on VLSI Systems, vol. 21, no. 10, pp. 1950-1954, Oct. 2013.

                                                                          

，    Sewook Hwang, Jabeom Koo, Kisoo Kim, and Chulwoo Kim, "A 0.008mm2 500 /spl mu/W 469kS/s Frequency-to-Digital Converter Based

CMOS Temperature Sensor with Process Variation Compensation," IEEE Transactions on Circuits and Systems I, vol. 60, no. 9, pp. 2241-2248,

Sep. 2013.

　

，    Jungmoon Kim and Chulwoo Kim, "High -Performance Wide-VDDH-Range Level Converter for Mixed-Signal Systems," IET Electronics Letters,

vol. 49, no. 18, pp. 1125-1126, Aug. 2013.

　

，    Jungmoon Kim and Chulwoo Kim, "A DC-DC Boost Converter with Variation Tolerant MPPT Technique and Efficient ZCS Circuit for

Thermoelectric Energy Harvesting Applications," IEEE Transactions on Power Electronics,  vol. 28, no. 8, pp. 3827-3833, Aug. 2013.

　

，    Minyoung Song, Sunghoon Ahn, Inhwa Jung, Yongtae Kim, and Chulwoo Kim, "Piecewise Linear Modulation Technique for Spread

Spectrum Clock Generation," IEEE Transactions on VLSI Systems, vol. 21, no. 7, pp. 1234-1245, Jul. 2013.

　

，    Hoonki Kim, Young-Jae Min, Chan-Hui Jeong, Kyu-Young Kim, Chulwoo Kim, and Soo-Won Kim "A 1mW Solar-Energy-Harvesting Circuit

using an Adaptive MPPT with a SAR and a Counter," IEEE Transactions on Circuits and Systems II, vol. 60, no. 6, pp. 331-335, Jun. 2013.

　

，    Hoonki Kim, Sangjin Kim, Chan_keun Kwon, Young-jae Min, Chulwoo Kim, and Soo-Won Kim, "An Energy-Efficient Fast Maximum Power Point

Tracking Circuit in an 800-uw Photovoltaic Energy Harvester," IEEE Transactions on Power Electronics, vol. 28, no. 6, pp. 2927-2935, Jun. 2013.

　

，    Soo-Bin Lim, Sewook Hwang, Jung-Taek You, Younghyun Baek, and Chulwoo Kim, "Current Adjustable Clock Distribution Network

Scheme for GDDR5," IET Electronics Letters,  vol. 49, no. 11, pp. 689-691, May 2013.

　

，    Soo-Bin Lim, Hyun-Woo Lee, Junyoung Song, and Chulwoo Kim, "A 247uW 800Mb/s/pin DLL-Based Data Self-Aligner for Through

 Silicon Via (TSV) Interface," IEEE Journal of Solid-State Circuits, vol. 48, no. 3, pp. 711-723, Mar. 2013.

　

，    Sewook Hwang, Kyeong-Min Kim, Jungmoon Kim, Seon-Wook Kim, and Chulwoo Kim, "A Self-Calibrated DLL-based Clock Generator for an Energy-Aware EISC Processor,"  IEEE Transactions on VLSI Systems, vol. 21, no. 3, pp. 575-579, Mar. 2013.

　

，    Junyoung Song, Inhwa Jung, Minyoung Song, Young-Ho Kwak, Yongtae Kim, Phi-Hung Pham, and Chulwoo Kim,  "A 1.62Gb/s-2.7Gb/s

Referenceless Transceiver for DisplayPort v1.1a with Weighted Phase and Frequency Detection,"  IEEE Transactions on Circuits and Systems I,

vol. 60, no. 2, pp. 268-278, Feb. 2013.

　

，    Young-Ho Kwak, Yongtae Kim, Sewook Hwang, and Chulwoo Kim, "A 20Gb/s Clock and Data Recovery with a Ping-Pong Delay Line for

Unlimited Phase Shifting in 65nm CMOS Process,"  IEEE Transactions on Circuits and Systems I, vol. 60, no. 2, pp. 303-313, Feb. 2013.

　

，    Phi-Hung Pham, Jongsun Park, and Chulwoo Kim,  "Design and Implementation of an On-Chip Permutation Network for Multiprocessor

System-on-Chip," IEEE Transactions on VLSI Systems, vol. 21, no. 1, pp. 173-177, Jan. 2013.

　

，    Phi-Hung Pham, Phuong Mau, and Chulwoo Kim,  "An On-Chip Network Fabric Supporting Coarse-Grained Processor Array," 

IEEE Transactions on VLSI Systems, vol. 21, no. 1, pp. 178-182, Jan. 2013.

　

，    Young-Jae Min, Hoon-Ki Kim, Chulwoo Kim, and Soo-Won Kim "A 5-Bit 500-MS/s flash ADC using time-domain comparison," Journal of

Circuits, Systems and Computers, vol. 21, no. 8, pp.1240023(1-12), Jan. 2013.

　

2012

　

，    Junyoung Song, Inhwa Jung, Sewook Hwang, and Chulwoo Kim, "Self-impedance calibrated PVT-insensitive pseudo open drain

output driver without external resistors,"  IET Electronics Letters,  vol. 48, no. 22, pp. 1394-1395, Oct. 2012.

　

，   Young-Jae Min, Chan-Hui Jeong, Kyu-Young Kim, Won Ho Choi Jong-Pil Son, Chulwoo Kim, and Soo-Won Kim  " A 0.31-1GHz Fast

Corrected Duty-Cycle Corrector with Successive Approximation Register for DDR DRAM Applications,"  IEEE Transactions on VLSI

Systems, vol. 20, no. 8, pp. 1524-1528, Aug. 2012.

　

，    Hyun-Woo Lee, Hoon Choi, Beom-Ju Shin, Kyung-Hoon kim, Kyung-Whan Kim, Jaeil Kim, Kwang-Hyun Kim, Jong-Ho Jung, Jae-Hwan

Kim, Eun-Young Park, Jong-Sam Kim, Jong-Hwan Kim, Jin-Hee Cho, Namgyu Rye, Jung-Hyun Chun, Chulwoo Kim, Young-Jung Choi,

and Byong-Tae Chung, "A 1.0ns/1.0V delay-locked loop with racing mode and countered CAS latency controller for DRAM interfaces,"

IEEE Journal of Solid-State Circuits, vol. 47, no. 6, pp. 1436-1447, Jun. 2012.

　

，    Sewook Hwang, Minyoung Song, Youngho Kwak Inhwa Jung, and Chulwoo Kim, "A 3.5 GHz Spread-Spectrum Clock Generator with a

Memoryless Newton-Raphson Modulation Profile," IEEE Journal of Solid-State Circuits, vol. 47, no. 5, pp. 1199-1208, May 2012.

　

，    Young-Jae Min, Chan-Keun Kwon, Hoon-Ki Kim, Chulwoo Kim, and Soo-Won Kim, "A CMOS Magnetic Hall Sensor Using a Switched

 Biasing Amplifier," IEEE Sensors Journal, vol. 12, no. 5, pp. 1195-1196, May 2012.

　

，    Moo-Young Kim, Hokyu Lee, and Chulwoo Kim, "PVT Variation Tolerant Current Source with On-Chip Digital Self-Calibration," IEEE Transactions on VLSI Systems. vol. 20, no. 4, pp. 737-741, Apr. 2012.

　

，    Phi-Hung Pham, Jongsun Park, Phuong Mau, and Chulwoo Kim, "Design and Implementation of a Backtracking Wave-pipeline Switch to Support Guaranteed Throughput in Network-on-Chip," IEEE Transactions on VLSI Systems. vol. 20, no. 2, pp. 270-283, Feb. 2012.

　

，    Jihwan Kim, Jungmoon Kim, and Chulwoo Kim, "A Wide Input Range Hybrid DC-DC Conversion System for Solar Energy Harvesting
,"  IET Electronics Letters,  vol. 48, no. 1, pp. 39-41, Jan. 2012.

　

，    Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jong Ho Jung, Kyung Whan Kim, Nam gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, and Joong Sik Kih, "A 1.6V 1.4Gbps/pin Consumer DRAM with Self-Dynamic Voltage Scaling Technique in 44nm CMOS Technology," IEEE Journal of Solid-State Circuits, vol. 47, no. 1, pp. 131-140, Jan. 2012.

　

2011

　

，    Jungmoon Kim, Jihwan Kim, and Chulwoo Kim,  "A Regulated Charge Pump with Low-Power Integrated Optimum Power Point

 Tracking Algorithm for Indoor Solar Energy Harvesting,"  IEEE Transactions on Circuits and Systems II, vol. 58, no. 12, pp. 802-806, Dec.

 2011.

　

，    Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Byung-Joo Yoo, Daeyun Shim, Chulwoo Kim, and Deog-Kyoon Jeong, "250Mbps-

5Gbps Wide-Range CDR with Digital Vernier Phase Shifting and Dual Mode Control in 0.13um CMOS ,"  IEEE Journal of Solid-State

Circuits, vol. 46, no. 11, pp. 2560-2570, Nov. 2011.

　

，    Moo-Young Kim, Jinwoo Kim, Tagjong Lee, and Chulwoo Kim, "10-bit 100-MS/s Pipelined ADC Using Input-Swapped Opamp Sharing and Self-Calibrated V/I Converter," IEEE Transactions on VLSI Systems, vol. 18, no. 8, pp. 1438-1447, Aug. 2011.

　

，    Inhwa Jung, Daejung Shin, Taejin Kim, and Chulwoo Kim, "A 140Mbps to 1.96Gbps Referenceless Transceiver with 7.2レs Frequency

 Acquisition Time,"  IEEE Transactions on VLSI Systems. vol. 19, no. 7, pp. 1310-1315, Jul. 2011.

　

2010

　

，    Sunghwa Ok, Kyunghoon Chung, Jabeom Koo, and Chulwoo Kim, "An Anti-Harmonic, Programmable DLL-based Frequency Multiplier for Dynamic Frequency Scaling," IEEE Transactions on VLSI Systems. vol. 18, no. 7, pp. 1130-1134, Jul. 2010.

　

，    Young-Ho Kwak, Inhwa Jung, and Chulwoo Kim, "A Gbps+ Slew-Rate/Impedance Controlled Output Driver with Single-Cycle Compensation Time," IEEE Transactions on Circuits and Systems II. vol. 57, no. 2, pp. 120-125, Feb. 2010.

　

，    Youngsun Han, Peter Harliman, Seon Wook Kim, Jong-Kook Kim, and Chulwoo Kim, "A novel architecture for block interleaving algorithm in MB-OFDM using mixed radix system," IEEE Transactions on VLSI Systems. vol. 18, no. 6, pp. 1020-1024, Jun. 2010.

　

2009

　

，    Inhwa Jung, Daejung Shin, Taejin Kim, and Chulwoo Kim, "A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays," IEEE Transactions on Circuits and Systems II, vol. 56, no. 10, pp. 773-777, Oct. 2009.

  

，    Moo-Young Kim, Dongsuk Shin, Hyunsoo Chae, and Chulwoo Kim, "A Low-Jitter Open-Loop All-Digital Clock Generator with Two-Cycle Lock-Time," IEEE Transactions on VLSI Systems, vol. 17, no. 10, pp. 1461-1469, Oct. 2009.

　

，    Dongsuk Shin, Janghoon Song, Hyunsoo Chae, and Chulwoo Kim, "A 7ps Jitter 0.053mm2 Fast Lock All-Digital DLL with Wide Range and High Resolution DCC," IEEE Journal of Solid-State Circuits, vol. 44, no. 9, pp. 2437-2451, Sep. 2009.

　

，    Jabeom Koo, Sunghwa Ok, and Chulwoo Kim, "A Low-Power Programmable DLL-Based Clock Generator with Wide-Range Anti-harmonic Lock," IEEE Transactions on Circuits and Systems II, vol. 56, no. 1, pp. 21-25, Jan. 2009.

　

2008

　

，    Jin-Seock Ma, Hyun Cheol Koo, Joonyeon Chang, Hyung-Jun Kim, Suk-Hee Han, Jonghwa Eom, and Chulwoo Kim, "Spin Hall Effect Induced by a Pd/CoFe Multilayer in a Semiconductor Channel," Journal of the Korean Physical Society,  vol. 53, no. 3, pp. 1357-1361, Sep. 2008.

  

，    Hyunho Chu, Jungmoon Kim, and Chulwoo Kim, "A monolithic voltage-mode DC-DC converter with a novel oscillator and ramp generator," IEICE Electron. Express. Vol. 5, No. 17, pp. 683-688, Sep. 2008.

  

，    Jaegeun Oh, Seok Joong Hwang, H. Giang Nguyen, Areum Kim, Seon Wook Kim, Chulwoo Kim, and Jong-Kook Kim, "Exploiting Thread-Level Parallelism in Lockstep Execution by Partially Duplicating a Single Pipeline," ETRI Journal, vol. 30, no. 4, pp. 576-586, Aug. 2008.

  

，    Dongshuk Shin, Soo-Won Kim, and Chulwoo Kim, "Wide frequency range duty cycle correction circuit for DDR interface," IEICE Electronics Express, vol. 5, no. 8, pp. 254-259, Apr. 2008.

  

，    Inhwa Jung, Gunok Jung, Janghoon Song, Moo-Young Kim, Junyoung Park, Sung Bae Park, and Chulwoo Kim,  "A 0.004mm2 Portable Multiphase Clock Generator Tile for 1.2GHz RISC Microprocessor," IEEE Transactions on Circuits and Systems II, vol. 55, no. 2, pp. 116-120, Feb. 2008.

  

2007

　

，    Gilsu Kim, Chulwoo Kim, and Soo-won Kim, "An automatic threshold-converged CMOS optical receiver for  high-definition digital audio interfaces," IEICE Electron Express, vol. 4, no. 22, pp. 690-695, Nov. 2007.

  

，    Gilsu Kim, Chulwoo Kim, and Soo-won Kim, "A CMOS Optical Receiver with Subtraction-Based Level Shifter for High-Definition Digital Audio Interfaces," Analog Integrated Circuits and Signal Processing, Springer, vol. 51, no. 3, pp. 169-173, June 2007.

  

，    Inhwa Jung, Moo-Young Kim, and Chulwoo Kim, "SPTPL : A New Pulsed Latch Type Flip-Flop in High-Performance System-on-a-Chip (SoC)," Journal of Circuits Systems and Computers, vol. 16, no. 2, pp. 169-179, Apr. 2007.

  

，    Dongkyu Park, Seok Soo Yoon, Inhwa Jung, and Chulwoo Kim, " Noise-aware Split-path Domino Logic and Its Clock Delaying," Journal of Circuits, Systems, and Computers, vol. 16, no. 1, pp. 139-154, Feb. 2007.

　

2006

　

，    Jin-Han Kim, Young-Ho Kwak, Moo-Young Kim, Soo-Won Kim, and Chulwoo Kim, "A 120MHz-1.8GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling," IEEE Journal of Solid-State Circuits, vol. 41, no. 9, pp. 2077-2082, Sep. 2006.

　

，    Inhwa Jung, Moo-young Kim, Dongsuk Shin, Seon Wook Kim, and Chulwoo Kim, "A New Energy x Delay-Aware Flip-Flop," IEICE Trans. Fundamentals, vol. E89-A, no. 6, pp. 1552 - 1557, Jun. 2006.   

 

2005

　

，    Youngsun Han, Seon Wook Kim, and Chulwoo Kim, "Jaguar: A Compiler Infrastructure for Java Reconfigurable Computing," ICESS, Lecture Notes in Computer Science 3820, Xian, China, vol. 3820 pp. 386 - 397, Dec. 2005.     

 

，    Tae-Chan Kim, Chulwoo Kim, Bong-Young Chung, and Soo-Won Kim, "A Low Power Cache with Successive Tag Comparison Algorithm," Current Applied Physics, vol. 5, no. 3, pp. 227 - 230, Mar. 2005.
　

2004

　

，    In-Chul Hwang, Chulwoo Kim, and Sung-Mo Kang, "A CMOS Self-Regulating VCO with Low Supply Sensitivity,"  IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 42 - 48, Jan. 2004.

 

2003

　

，    Tae-Chan Kim, Seok-Joon Park, Bong-Young Chung, Chulwoo Kim, and Soo-Won Kim, "Design of a Response Time Accelerator for an LCD Panel," Journal of the Korean Physical Society, vol. 43, no. 5, pp. 858-862, Nov. 2003.
　

，    Jaegeun Oh, Seon Wook Kim, and Chulwoo Kim, "OpenMP and Compilation Issues in Embedded Applications," Lecture Notes in Computer Science, vol. 2716, pp. 109-121, Jun. 2003.

 

，    Chulwoo Kim, Kiwook Kim, and Steve Kang, "Energy-efficient Skewed Static Logic(S2L)with Dual Vt: Design and Synthesis," IEEE Tran on VLSI Systems, vol. 11, no. 1, pp. 64-70, Feb. 2003.

 

~2002

　

，    Chulwoo Kim, In-Chul Hwang, and Steve Kang, "A Low-Power Small-Area ‐7.28 ps Jitter 1-GHz DLL-based Clock Generator," IEEE Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1414-1420, Nov. 2002.

 

，    Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, and Steve Kang, "High-Speed CMOS Circuits with Parallel Dynamic Logic and Speed-enhanced Skewed Static Logic," IEEE Tran. on Circuits and Systems ゛, vol. 49, no. 6, pp. 434-439, Jun. 2002.

　

 ，    Chulwoo Kim and Steve Kang, "A Low-Swing Clock Double Edge-Triggered Flip-Flop," IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 648-652, May 2002.

 

，    Chulwoo Kim, Seung-Moon Yoo, and Steve Kang, "Low Power Adiabatic Computing with NMOS Energy Recovery Logic," IEE Electronics Letters, vol. 36, no. 16, pp. 1349-1350, Aug. 2000.

　

，    Chulwoo Kim and Soowon Kim, "Wired-OR Property and Improved Structure of Recovered Energy Logic (REL)," IEE Electronics Letters, vol. 33, no. 9, pp. 760-762, 1997.